1. Field of the Invention
The present invention relates to semiconductor circuit devices and more specifically to a semiconductor circuit device having active and standby states.
2. Description of the Background Art
Prior Art 1
In miniaturizing transistors, power supply voltage is not always scaled down in accordance with the scale-down of a device but power supply voltage may remain constant when a device size is reduced. In this case, electric field strength in the vicinity of a drain increases. Accordingly, hot carriers are generated in a channel and injected into a gate oxide film, thereby deteriorating the characteristics of a transistor element. One method of solving this problem is called NOEMI (Normally-On Enhancement MOSFET Insertion). FIG. 40 shows one example of NOEMI. In this example, an N channel MOS transistor Qn2 is provided between the drain terminal of an N channel MOS transistor Qn1 and the output node of an inverter formed of a P channel MOS transistor Qp1 and N channel MOS transistor Qn1. Since the voltage of Vcc is always applied to the gate of N channel MOS transistor Qn2, N channel MOS transistor Qn2 is always in the on state By thus providing N channel MOS transistor Qn2, the drain voltage of N channel MOS transistor Qn1 is limited to (gate voltage of N channel MOS transistor Qn2)−(threshold of N channel MOS transistor Qn2).
In a CMOS type semiconductor device, in accordance with miniaturization of a device, power supply voltage is decreased so as to ensure the reliability of the device and reduce power consumption. In order to achieve high speed operation in this situation, the threshold of each MOS transistor needs to be lowered in accordance with the decreased power supply voltage. In this case, a subthreshold current flowing between a source and a drain when a transistor is in the off state increases. This increases a direct current in the entire large scale integration and especially increases a standby current in a dynamic semiconductor memory device. One method of solving this problem is the MT-CMOS (Multi-Threshold CMOS) configuration. One example of the MT-CMOS configuration will be described with reference to FIG. 41. An N channel MOS transistor Qn11 having a threshold (Mid-Vth) higher than that of a transistor in a CMOS inverter C1 is provided in series with inverter C1 operating at a low threshold. By controlling a control signal φ so that N channel MOS transistor Qn11 is turned on in an active state and turned off in a standby state, inverter C1 operates at high speed in the active state and the subthreshold current is decreased in the standby state.
Prior Art 2
One method capable of achieving the same effect as the MT-CMOS is to decrease a subthreshold current by causing the gate potential of N channel MOS transistor Qn11 shown in FIG. 41 to be a minus potential in the standby state.
Prior Art 3
In typical memory LSIs and logic LSIs, most node voltages are often predetermined in the standby state. As described in Very Large Scale Integration Memory, (1994), Baifukan S1, p. 365, there is a method to decrease a subthreshold current in the standby state by a logic circuit having a hierarchical configuration of power supplies. FIG. 42 is a block diagram showing one example of the logic circuit structure. The logic circuit includes an inverter IVL connected between a main power supply line MVcc and a sub ground line subGND and receiving an L level input signal in the standby state, an inverter IVH connected between a sub power supply line subVcc and a main ground line MGND and receiving an H level input signal in the standby state, a P channel MOS transistor Qp21 connected between main power supply line MVcc and sub power supply line subVcc and turned on/off in response to a control signal /φ, and an N channel MOS transistor Qn21 connected between main ground line MGND and sub ground line subGND and turned on/off in response to a control signal φ. Control signal φ is at the L level in the standby state and at the H level in the active state.
The thus structured logic circuit has its P channel MOS transistor Qp21 and N channel MOS transistor Qn21 turned off in the standby state. Accordingly, a subthreshold current flowing between the output node of inverter IVL and sub ground line subGND and a subthrreshold current flowing between the output node of inverter IVH and sub power supply line subVcc are decreased. In the active state, Qp21 and Qn21 are on and the logic circuit performs a normal operation.
Prior Art 4
As the operating voltage and threshold voltage of a transistor decrease, it comes to be difficult to ignore a subthreshold current in the active state as well. Especially in a circuit block in which a large number of the same circuits are repeated as in driving circuits of word drivers, decoders and sense amplifiers and a small number of them are selected to operate, a subthreshold current continues to flow in a large number of non-selected circuits. A method to solve this problem is described in Very Large Scale Integration Memory, (1994), Baifukan, p. 367. FIG. 43 is a block diagram showing one example of the method. According to the method, a circuit is divided into a plurality of blocks BKi (i=1−n), and switch transistors PSWi are provided between sub power supply lines subVcci for respective blocks BKi and main power supply line MVcc. Only switch transistor PSWm corresponding to a selected block BKm is turned on and other switch transistors PSWi are turned off to decrease a subthreshold current flowing in non-selected blocks.
Problem with Prior Art 1
In the circuit of the NOEMI configuration, N channel MOS transistor Qn2 is always in the on state as shown in FIG. 40. When the threshold of N channel MOS transistor Qn1 is decreased, the subthreshold current flowing between output node OUT and ground node GND in the standby state thus increases.
Problem with Prior Art 2
In practice, the subtrheshold current is substantially varied by variation in the threshold of a transistor caused when manufactured. Since the level of the minus voltage applied to the gate of N channel MOS transistor Qn11 is constant, the variation in the transistor threshold prevents the subthreshold current from efficiently being decreased, lowers the operating speed of the circuit even when the subthreshold current can be decreased, and so on.
Problem with Prior Art 3
In the circuit having hierarchical power supply lines and ground lines, the capacitance of the sub power supply line and the sub ground line increases. As a result, the sub power supply line and the sub ground line do not always have a power supply potential or a ground potential immediately after a power supply is turned on or immediately after a transition from the standby state to the active state. Accordingly, there caused problems such as a malfunction due to a timing mismatch and consumption of a peak current.
Problem with Prior Art 4
The circuit structure as shown in FIG. 43 requires substantial time from block selection to sufficient precharging of a sub power supply line in the block. The internal circuit in a selected block may operate even when its sub power supply line is not sufficiently precharged. Accordingly, there caused problems such as an access time delay and a malfunction.